Design Implementation and Verification of a Flexible I3C Hardware Architecture

The emergence of the Improved Inter-Integrated Circuit (I3C) protocol has led to a proliferation of products featuring I3C interfaces in the market. However, existing I3C devices often suffer from limited compatibility and adaptability. To tackle these issues, this paper proposes a flexible hardware architecture specifically designed for I3C. The architecture is built upon configurable and reusable components integrated within the hardware design, enabling upper-layer software to dynamically adjust the behavior and functionality of the I3C interface via hardware registers. This approach effectively meets the diverse requirements of I3C peripheral device chips. After a comprehensive design and functional verification, the developed I3C module is confirmed to operate correctly, achieving a code coverage of 99.02% and functional coverage of 100%.