A 4-to-16GHz Dual-Loop PLL Based on Current-Control RO and Calibration in a 6-nm FinFET

This work presents a PLL design in an advanced 6- nm FinFET CMOS technology and proposes a strategy for designing a ring-based PLL with low jitter and reference spur performance. With calibration function, the ring-based PLL achieves
$420-\text{fs}_{\text{rms}}$
integrated jitter and reference spurs at -68 dBc, which can meet the low noise requirements of 32Gbps SerDes. The PLL has an active area of 0.015 mm2, consuming 4.9 mW from a 0.75V supply at 16GHz, translating to a figure of merit of -240.6 dB.