Shift Power Reduction in High-Performance Clock Network Designs

With the rapid development of deep submicron (DSM) high-performance VLSI circuits, building a robust clock tree with minimal insertion delays, skews and jitter has turned out to be challenging. Several techniques have been developed to reduce the clock insertion delay & clock skew. A few such techniques are Clock Mesh CTS, Multi Source CTS or Multi Entry CTS. These techniques help reduce insertion delays, skews and jitter across the design but can adversely affect the power since the significant section of a design driven by a clock source can toggle within a short time. Impact will be higher during the scan shift phase where all clock gating circuits are transparent in blocks targeted for ATPG. Due to a significant reduction in insertion delay and clock skew, the clock edge reaches all the sinks in design quickly resulting in a significant amount of activity happening in a short span of every shift clock edge. In this paper, we discuss the adverse effects of high-performance clock network schemes on Shift power and techniques to save Shift power in such scenarios. Results from the analysis of a few blocks will also be shared. Solution described in this paper is applicable in high performance designs where clock mesh clock tree network architectures are implemented.