An FPGA Based Emulation of Source Synchronous Protocol-Aware Timing Stress Test

This paper discusses about an FPGA based emulation of source synchronous protocol-aware hardware which can be used to test the timing parameters of various medium speed protocols on silicon. Due to the multi-instance and multi-site test capability of the proposed method, the test time of SPI timing parameters reduces by more than 15 times. It creates testability for erstwhile untestable timing parameters of SDHC and eMMC protocols.