A Hybrid Test Point Insertion Strategy for Improved Test Metrics

Rapid increase in design complexity and new defects in shrinking technology nodes have led to development of advanced fault models like cell-aware, small delay defects., etc., resulting in an increase of cumulative patterns required for screening the devices to achieve higher coverage targets. However, there is a growing need to reduce the cost of testing. The fine balance between improved test coverage and reduced pattern count has been traditionally addressed with test point insertion, but with an incurred area penalty. In this paper we will discuss a hybrid test point insertion technique which addresses the requirements of coverage, pattern volume and area.