A Formal Based Verification Methodology for DFD Mux-Tree Hierarchies

The increasing complexity of System-on-Chip (SoC) products has amplified the potential for design bugs, necessitating robust post-silicon validation to ensure system reliability. Design-for-Debug (DFD) infrastructure plays a pivotal role in providing observability to internal nodes during post-silicon debugging. However, the traditional verification of DFD's hierarchical multiplexer (mux) trees, which are essential for signal routing, is full of challenges. The legacy verification process is time-consuming, resource-intensive, and prone to human error, particularly in the manual assignment of unique identifiers (IDs) to muxes. This paper presents an innovative methodology that leverages Formal Verification and automated ID assignment to streamline the verification of SoC-level muxtrees. It replaces the laborious simulation-based approach with a more efficient formal verification process, reducing the verification time from 10 days to a single day. Additionally, the automated ID assignment algorithm ensures accuracy and consistency in the mux configuration, eliminating the risk of human error and the need for iterative manual efforts. The implementation of the proposed flow, and the significant improvements in verification efficiency demonstrated through experimental results by providing a scaled down version of the mux-tree in the case study.