Concurrent Low Power Built-in Self-Test for Safety Critical SoCs

In safety critical automotive devices, boot-up time and periodic checks of the correctness of logic and memory are of utmost importance for the overall operation of the device from safety perspective. Logic Built-in Self-Test (LBIST) and Memory Built-in Self-Test (MBIST) play a crucial role in ensuring the reliability and performance of safety-oriented chips. This paper first addresses the power concern of running both LBIST and MBIST parallelly and proposes novel architectures to minimize the power dissipation during LBIST and MBIST while ensuring that the target coverage is metwithin the acceptable test time. This paper then presents concurrent BIST architecture to parallelly perform LBIST and MBIST on safety islands to reduce the overall boot time which is critical to meet Automotive Safety Integrity Level (ASIL) standards.