UWB Low RMS Jitter Phase-Locked Loops Using Voltage-Controlled Oscillator

This paper presents an ultra-wideband (UWB) phase-locked loops (PLL) with a voltage-controlled oscillator (VCO), which is fabricated in a TSMC 1P6M 0.18 μm CMOS process. The PLL is composed of seven major blocks, locking frequency at 8.44808GHz within 1.8us. The tracking frequency range of PLL involves from 15.84MHz to 16.57MHz passing through the frequency multiplier, phase frequency detector, charge pump, LPF, VCO and Divide-by-2 injection-locked frequency dividers (ILFD), and digital divider in order to output frequency from 8.110GHz to 8.483GHz. The phase noise of VCO is −107.25 dBc/Hz@1MHz offset, and the total power dissipation of PLL is 76.82mW.