Co-Design of Interchiplet, Package, and System Interconnect Protocols

Artificial intelligence (AI) applications are adopting modular tile design paradigms for compute and networking chiplets. The integration of UCIe as a die-to-die interconnect for low latency and power savings allows a disaggregation of large monolithic dies. This paper covers interchiplet architectures that can be built toward a chiplet portfolio for escalating bandwidth needs in networking and AI/machine learning. The electrical layer of UCIe design verification is illustrated. In addition, the topic of package design and challenges associated with the integration of the physical layer, in both standard and advanced packaging, are discussed.