An SoC Based Hardware Accelerator for Blind Assistive System

In recent years, deep learning has been developing rapidly, and its applications have revolutionized various fields, especially in the field of computer vision, and have been practically applied to people's daily lives. In this paper, we design an assistive system for the blind and implement it on a system-on-chip (SoC) FPGA board. The system combines an object detection network and text-to-speech technology to make it easier for the blind to walk alone in unfamiliar environments. Considering the cost and power consumption in practical applications, we therefore perform hardware acceleration of the object detection neural network and combine FPGAs and ARMs to achieve a system-level access control design. The system is implemented on a Xilinx Zynq UltraSacle+MPSoC EGO-ZUI9EG FPGA, and the results show that the power consumption is 6.599W and the processing time is 1.3s when the frequency is 1 66MHz.