Propagation Time Minimization of the on-Chip Critical Signal Path

This paper demonstrates the propagation time minimization procedure in the digital CMOS circuits applied to the chain of logic gates in a critical path of the signal. Demonstrated procedure is based on the linear model for fast, first order, propagation time estimation. The model enables derivation of the algorithm easily translated to the physical dimensions of the gate's MOS-FET devices. Effectiveness of the presented algorithm is exemplified on the four-gate chain with branching, targeting the 180nm CMOS process node.