A Synthesizable Digital Frequency-Locked Loop Widely Tunable up to 640 MHz in 130 nm CMOS

Frequency-locked loops (FLLs) represent a viable way of generating a range of frequencies from a single reference frequency by using a negative feedback electronic control system that compares the frequency of a controlled oscillator to the reference one. A digital synthesizable FLL is designed in 130 nm CMOS technology for a target frequency of up to 640 MHz. It employs a wide-tuning range digitally controlled oscillator (DCO) assembled from tri-state inverters in the form of a matrix. The FLL can optionally use a bang-bang or a soft-programmable standard proportional-integral-derivative (PID) controller to regulate the feedback loop. Its design practically minimizes metastability occurrence. The proposed digital FLL occupies $\mathbf{100} \boldsymbol{\mu}\mathbf{m} \times \mathbf{330}\boldsymbol{\mu}\mathbf{m}$ and consumes 3.5 mW in typical operating conditions. The reference clock is 16 MHz, and the output oscillation frequency is set to 640 MHz, while the achieved frequency resolution is 2.8 MHz.