Study of Spacing-induced Fringing Effects on Emerging CFET Technology Nodes

This paper simulates CFET characteristics and its inverter performance at A
⁰
technology nodes using TCAD simulation. We demonstrate CFET inverter’s suitability for very low power consumption (0.2 V) and investigate reliability issues caused by fringing effects that retard corner currents through SRH recombination and current density simulations. This study investigates the separation thickness (D
pn
) of p- and n-CFETs as well as the distance between nanosheets (D
ns
) to explore the fringing effects, offering valuable design guidelines for CFET technology.