A Novel 2-Tier Stacked Vertical Channel GAA Transistor Architecture with Area-Saving 3-Dimensional Local Interconnect to Achieve Gb-Density 6T SRAM with Acceptable Low Standby Chip Leakage (~1mA)

Among memory devices, 6T SRAM stands out as the premier classic memory, offering the best switching speed and bandwidth performances. Although CMOS will continue to scale to ~1nm node, the scaled CMOS devices have quite high leakage currents that make Gb-density SRAM a very high-power consuming memory at standby. In this paper, we introduce a groundbreaking 2-tier stacked vertical-channel Gate-All-Around (GAA) device, achieving high-density SRAM equivalent to N1 node (simulation unit cell area ~0.006um
²
). A novel 3D local interconnect efficiently connects contacts and routing between 3 devices (PG, PU, PD) without footprint wastage. The vertical-channel device, with a long channel length (Lg=30nm) and suitable drain-gate offset (Ls=20nm), significantly reduces Gate-Induced Drain Leakage (GIDL) to ~0.2pA per transistor at Vcc. This enables designing a 1Gb standalone SRAM memory chip with affordable standby leakage at only ~1mA level, which is already smaller than DRAM refresh power. Very high-speed switching time (~ns) together with very low switching energy per bit (~31fJ/bit) can be achieved to meet ultra high-bandwidth memory.