First demonstration of SRAM transistor based on 3-dimensional stacked FET with back side interconnection structure beyond 1nm node

For the first time, we report SRAM transistor demonstration based on 3-Dimensional Stacked FET (3DSFET) with Back Side Interconnection (BSI) structure. The use of NMOS as top and PMOS bottom device structure provides advantage of preserving the bottom PMOS channel stress engineering. However, from the SRAM perspective, PG transistor changes from NMOS to PMOS because bottom device can’t be removed. By employing the BSI technology to reduce the cell height and Back-End-of-Line metal resistance, we propose using NMOS device for the PG as usual, achieving a 29% higher scalability for the SRAM bitcell, along with the most competitive SRAM performance with 28% higher IREAD and 3% WRM improvement.