On the Design of LDPC-Based Error-Reducing Codes

In this paper, we continue our investigation into the error-reducing properties of superposition codes started in Andreev, et al. (2023), where the focus was on Sparse Regression Codes (SPARCs) with Gaussian signals. However, despite their high performance, SPARCs are known to have noticeable limitations in their application due to their high decoding complexity. This prompted us to propose a Low-Density Parity Check (LDPC)-based superposition scheme with low-complexity Soft Successive Interference Cancellation (SIC) decoding. In this paper, we focus on such a scheme and perform a detailed analysis of it. We have developed a low-complexity quantized density evolution (DE) procedure for the proposed scheme under the SIC decoder to estimate the output bit error rate. It is shown that the obtained DE procedure quite accurately predicts the behavior of the considered LDPC-based superposition scheme. The procedure predicts not only the waterfall region, but also the error-floor region, which we assume to be caused by interference of component LDPC codes. This helps us to obtain highly optimized constructions of proto-graphs of LDPC code components and significantly improve the bit error rate performance of the whole construction. In addition, for the proposed scheme we have analyzed the output error count distribution, which is crucial for concatenated code constructions, where usually error-reducing codes are used as inner code. All numerical results and analysis are presented at the end of the paper.