An efficient hardware implementation of LED lightweight block cipher

New technologies like the Internet of Things (IoT), Radio Frequency Identification (RFID), and Wireless Sensor Networks pose unique challenges due to their limited power and real-time demands. Among these challenges, ensuring efficient and low-latency encryption systems is paramount. To address these challenges, lightweight encryption algorithms like LED cipher have emerged in recent years. LED offers a promising balance between efficiency and security, making it ideal for securing IoT devices. In the present work, we present two distinct hardware architectures for the LED block cipher tailored for devices with limited resources, employing a 32-bit data path. These architectures aim to optimize performance and resource utilization while maintaining robust security. The iterative architecture offers parallel processing for faster encryption/decryption but requires higher hardware resources, while the serial architecture sequentially performs operations to minimize resource consumption. Experimental results demonstrate the efficacy of the suggested hardware architectures, highlighting low latency and high throughput compared to existing hardware implementations of various block ciphers. Our findings indicate that both architectures provide efficient solutions for implementing the LED algorithm in resource-constrained environments.