FPGA implementation of Chaotic pseudo-random number generator for cryptographic applications

Reconfigurable systems often require secret keys for encrypting and decrypting data. To address this need, applications requiring high security typically use physical unclonable functions (PUFs) - circuits that leverage random manufacturing variations to generate unique secret keys for each device. However, implementing PUFs on field-programmable gate arrays (FPGAs) can be challenging due to limited control over the layout. An alternative approach is the use of chaos-based random number generators, which are widely employed in chaos-based encryption and security applications. These generators provide a fast, deterministic source of randomness for operations like permutation and substitution. This paper presents an FPGA-based Chaotic Key Generator (C-KG) that is based on the Lorenz, Rossler, Chen, and Chua chaotic systems. Each system was implemented and tested for Pseudo Random Number Generation. Moreover, the proposed C-KG was implemented using VHDL and synthesized on a Zynq ZedBoard FPGA. The generator’s randomness, keyspace, and operations per bit ratio for each chaotic system using the NIST 800-22 statistical test suite have been assessed to validate the proposed approach. The C-KG was found to utilize minimal resources of the FPGA’s slices, operate at frequencies up to 190.548 MHz, and successfully pass all NIST statistical tests.