FPGA Implementation of Robust and Secure Transmission Cryptosystem for Satellite Images

In today’s interconnected world, with the changes caused by the technological revolution conflicts, politics, diseases and climate changes, along with the growing influence of artificial intelligence (AI), the threat of manipulating data is on the rise. In the field of satellite imagery, data transfer security is especially crucial. One of the most important tools for safeguarding satellite images during storage and transmission is cryptography. It offers an imperceptible substitute to quick response codes. The literature focuses predominantly on software implementations of encryption techniques, despite scenarios where hardware cryptographic solutions are preferable or necessary due to increased requirements for speed, power, or data security. IP cores offer a versatile and widely applicable solution for hardware development, serving as the basic building blocks for constructing processors on field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). This paper presents an innovative embedded chaotic algorithm designed to enhance the security of satellite images by integrating Ribonucleic Acid (RNA)-encoded encryption, Fisher-Yates shuffling and the Fractional order 4D Chen system. To achieve an optimal balance between encryption time and security, the original image undergoes strategic block division, with each block undergoing encryption via a series of steps including XOR operations, RNA dynamic encoding and decoding, RNA dynamic operation rules, and Fisher-Yates shuffle. The primary objective of this study is to enhance the efficiency and speed of the encryption process by presenting the realisation of a robust cryptographic scheme in the form of an IP core tailored which has been implemented on ZedBoard FPGA using the Vivado High-Level Synthesis (HLS) design suite. By utilising the hardware parallelism intrinsic to FPGA architectures, we attain significant enhancements in execution time compared to the software-based implementation (frequency of 160.01 MHz). Experimental and analytical results demonstrate the algorithm’s robust security, resilience to single-event upsets, large key space, and low time complexity.