Accelerating AES in 5G Security Protocols: A System-Level FPGA Implementation

In this research work, we address the necessity of accelerating 5G cryptography and present a Field-Programmable Gate Array (FPGA) Implementation of a system-level acceleration scheme for the advanced encryption standard (AES) algorithm in 5G Packet Data Convergence Protoco (PDCP) cryptography. The solution includes the design and implementation of the user-space module, the kernel-space module, and the FPGA module, utilizing a data path based on Peripheral Component Interconnect Express (PCIe) between the host and the FPGA. Results show FPGA-based acceleration scheme can achieve 35.9 times at most at unit tests and improve by 488.75 Mbps at most in the real wireless communication environment compared to the pure C-based implementation.