On-Chip ESD Protection: Device Innovation

Electrostatic discharge (ESD) failure is a major integrated circuit (IC) reliability problem. On-chip ESD protection has drawn continuous R&D efforts for decades and becomes increasingly challenging for modern chips at advanced technology nodes where ESD protection device structures play foundational roles. This paper reviews key device innovation in modern on-chip ESD protection designs, leading to future ESD protection perspectives. Chip-level ESD design innovation, including ESD design methodologies, will be reviewed separately.