A Programmable 5G DU-RU SmartNIC based on MPSoC FPGA

The adoption of disaggregated, virtualized, and open gNodeB in the next generation Radio Access Network offers benefits such as cost reduction and improved network performance. However, meeting specific 5G and beyond requirements, e.g., Ultra Reliable Low Latency Communications, requires offloading selected gNodeB functions onto accelerated hardware. This study proposes to implement a 5G Distributed Unit (DU)Radio Unit (RU) in a System-on-a-Programmable-Chip (SoPC) where the FFT of Orthogonal Frequency Division Multiplexing in uplink transmission is offloaded onto an FPGA. The proposed solution is programmable and pluggable, allowing flexibility in function implementation and integration into various devices. The experimental evaluation shows that the proposed SmartNIC-based DU-RU achieves $15 \times$ speedup in processing time when compared to a server’s CPU with FPGA-accelerated Low-PHY processing. In addition, it shows that employing highperformance off-chip memory leads to about $14 \%$ reduction in processing time compared to the use of an FPGA-internal block memory.