A Reconfigurable Computing-in-Memory Accelerator With Dynamic Group-Based Dataflow and Dual-Input Macro Designs

Non-volatile memory-based computing-in-memory (nvCIM) is a promising candidate for accelerating deep neural networks (DNNs) at the edge. However, current nvCIMs adopt fully-pipelined (FP) or layer-serial (LS) dataflows for all DNN layers, suffering poor area and energy efficiency for the layer-wise-varied workloads. Furthermore, their fixed macro structure results in resource under-utilization, as it is unable to adapt to varying weight sizes. To address these issues, this brief proposes a reconfigurable nvCIM with dynamic dataflow. First, it contains a dynamic inter-pipelined-intra-serial (IPIS) dataflow with group partition mechanism, adapting to the diverse workloads for high area and energy efficiency. Second, it has a dual-input block-reconfigurable (DIBR) macro structure, allowing finer granularity input selection to improve macro utilization and achieve input data reuse. When applied to four well-known networks, the proposed design attains $2.27\sim 11.92\times $ area efficiency gains and $2.21\sim 14.43\times $ energy efficiency gains over nvCIM baselines.