A Design of 10 – 16 GHz CMOS High Spectral Purity Frequency Quadrupler

This paper presents the implementation of a frequency quadrupler operating in the 10-16 GHz range using 65-nm CMOS technology. The quadrupler comprises two cascaded push-pull doublers (PPD) and two 1-bit elliptic bandpass filters (BPF) for harmonic filtering. The interleaved BPFs effectively suppress undesired harmonics, resulting in a high harmonic rejection ratio (HRR). Measurement results demonstrate a worst-case output HRR exceeding 27 dBc across the 10-16 GHz frequency range with an input power of 2.5 dBm. The quadrupler exhibits a minimum conversion loss of 3.8 dB, corresponding to a maximum output power of -1.3 dBm. The chip occupying an area of 1.89 mm
²
consumes 65 mW with a 1.2 V power supply.