Implementing Convolutional Auto Encoder on FPGA using High Level Synthesis

This study introduces a CNN-based Autoencoder implementation on FPGA using High-Level Synthesis (HLS), focusing on optimizing convolutional computing for reduced latency and enhanced resource efficiency. Implemented on the FPGA, the design utilizes 69,407 Flip-Flops (FFs), 104,467 Look-Up Tables (LUTs), and 3,716 Digital Signal Processors (DSPs), achieving an operational frequency of 100 MHz and a latency of 0.15 milliseconds. Through techniques such as pipelining, parallelization, and loop unrolling, we navigate the balance between resource utilization, computational speed, and image reconstruction fidelity. Our findings demonstrate the potential of HLS for efficiently deploying deep learning models on hard-ware, offering valuable insights for advancements in real-time processing applications.