A 70dB SNDR Continuous-Time Sigma-Delta Modulator in Sub-GHz Communication System

A low-power second-order continuous-time sigma-delta modulator for analog to digital converter (ADC) in SubGHz transceiver is presented. The modulator is designed in a 55nm CMOS technology. Simulation results show that the modulator achieves 70dB SNDR which corresponds to 11.3 bits ENOB for an OSR of 128 over a 1MHz signal bandwidth. The total power consumption is 2.2mW from a 1.2V supply and the overall active core area is 0.026 mm2.