Design of a Rail-to-rail 12-Bit 2.5-MSPS SAR ADC with Low-area on 180nm CMOS Process

The Successive Approximation Register Analog-to-digital Converter (SAR ADC) in this research utilizes a simple structure to save area while maintaining good operational performance nearly equivalent to other more complex structures. The SAR ADC was entirely designed based on an analog IC design process, with the digital blocks within this SAR ADC also being implemented at the transistor level for design optimization and area saving. The structure of the single-ended algorithm enhanced the feasibility of the design, especially when designing digital blocks in the analog circuit design process. To address the major drawback of the single-ended SAR ADC, which was rail-to-rail input, the authors also proposed models for the internal components of the SAR ADC. The proposed SAR ADC was implemented on 180nm CMOS process. The SAR ADC had an input range from 439μV to 1.7996V and an output resolution of 12-bit at a sampling rate of 2.5-MS/s and a supply voltage of 1.8V. The ADC achieved a Figure of Merit (FoM) of 989 fJ/Conv.-step due to SNDR of 57.32dB, SFDR of 62.05dB, and 1.486mW power consumption. The active area of the ADC core is only 521μm x 57.82μm, equivalent to 0.03mm
²
.