A Novel NoC-based SNN Architecture with Optimized Routers

Spiking Neural Networks (SNNs), with their efficient energy usage, have gained prominence in AI hardware inference tasks. One of the major challenges regarding the implementation of SNN using a Network-on-Chip (NoC) architecture is the handling of packet routing, a mechanism to send and receive packets among the neuron cores of the network. For many of the proposed SNN NoC-based architectures, the routing components are integrated inside cores, which leads to significant resource consumption and latency issues, particularly in large-scale net-works. This paper addresses these challenges by introducing a novel NoC-based SNN architecture, in which routers are externalized outside of the cores, each linked to four adjacent cores and surrounding routers in the network grid. This approach helps to reduce resources significantly in large networks, in which the number of routers takes up a considerable proportion. Specifically, our approach results in the hardware resource reduction of 17.88% Look-Up Table and 36.91% Flip-flops. This also leads to a 5.68% decrease in the power consumption.