Fast-Locking Phase Locked Loop Dominated by SMC at VCO Voltage Tuning End

The presented fast-locking phase-locked loop (PLL) approach, driven by sliding mode control (SMC), aims to maintain defined design parameters and system stability while achieving faster frequency switching. By adding the SMC output control voltage to the tuning terminal of the voltage controlled oscillator (VCO), the PLL system achieves a higher absolute rate of change of the VCO output frequency during frequency hopping. Simulation results in Simulink demonstrate a significant reduction in locking time, from
$40~\mu \text {s}$
in the conventional PLL to
$5~\mu \text {s}$
in the proposed PLL, under identical conditions of loop bandwidth and charge pump current.