A Review of Literature on Memory Structures

Summary

This chapter discusses the importance of memory in computing systems, particularly in the context of the increasing number of devices connected to the Internet. It highlights the need for large amounts of memory to support the growing scale of calculations. This chapter explores the advancements in static RAM (SRAM) production, which have led to reduced bit‐cell area and improved efficiency through innovations in circuit lithography. The design and optimization of nanoscale SRAM are emphasized, taking into account design limitations, stress, and approximation. Techniques such as using the minimum supply voltage, improving write/read operations, and reducing leakage are employed to achieve high performance. The reliability of SRAM arrays is addressed through architecture‐dependent techniques and other methods like parity protection, error correction codes, and redundancy. The impact of process variations on RAM bit‐cells is discussed, with variations such as line‐edge roughness (LER) and random dopant fluctuations posing challenges to nanodimensional designs. This chapter also highlights the potential of quantum dot cellular automata (QCA) technology, which offers benefits like reduced dimensions, low energy consumption, and high switching speed. The optimal design of memory units and SRAM cells in QCA technology is considered crucial. Two common memory designs, line‐based memories and loop‐based memories, are introduced. The book focuses on presenting new binary and ternary designs for the loop‐based PIM (processing in memory) approach. Flip‐flops, RAM cells, and the PIM architecture are discussed as basic memory structures in binary QCA. This chapter also introduces the concept of Akers logic arrays, which are two‐dimensional arrays of logic cells connected in a rectangular grid. Akers logic arrays can perform computations in memory and are considered a basic structure for PIM. The stripping process is explained as a method for calculating the output of the Akers array. The literature review section provides an overview of QCA‐based memory designs, specifically loop‐based and line‐based memory structures. This chapter references studies on hybrid memory architectures, new D‐FF structures, and other memory design approaches. Overall, covers various aspects related to memory design, including advancements in SRAM production, design optimization, reliability considerations, the potential of QCA technology, and different memory structures and their applications. The fault‐tolerant, three‐input majority gates were investigated.