3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size ($\mathbf{25}\times \mathbf{33}\mathbf{mm}^{\mathbf{2}}$) Single-Crystalline Si on SiO2 by Elevated-Epi

The Elevated Epi technique is presented for the fabrication of single-crystal (100) silicon of wafer field size (25mmx33mm) for monolithic three-dimensional integrated circuits (3DICs). Elevated Epi uses a low substrate temperature, pulse laser technique to fabricate single-crystal Si on dielectric. We also demonstrate 3D inverters, with an inter-layer metal M0 positioned between two layers of FinFETs. A hybrid-3D cell library is presented for improving performance, power, and area of 3DICs.