A Stochastic Analog SAT Solver in 65nm CMOS Achieving $\mathbf{6.6}\mathbf{\mu}\mathbf{s}$ Average Solution Time with 100% Solvability for Hard 3-SAT Problems

This paper presents a stochastic analog SAT solver, featuring a fast open-loop architecture with continuous-time self-loopback pull-up switches, a discrete-time scrambling scheme, and a cost-efficient hybrid random code generator. The SAT prototype in 65nm CMOS achieves orders of magnitude improvement in speed and energy efficiency compared to prior ASIC (digital and analog) SAT solvers.