A 48-Gb/s Half-Rate PAM4 Optical Receiver with 0.27-pJ/bit TIA Efficiency, 1.28-pJ/bit RX Efficiency, and 0.06-mm2 area in 28-nm CMOS

This work presents a 48-Gb/s PAM4 optical receiver with TIA and sampler integrated. The TIA employs transadmittance transimpedance (TAS-TIS) structure to replace conventional CML-based VGA and post-amplifier, eliminating CTLE and inductive peaking while preserving the linearity and the gain-bandwidth product for PAM4 operation. The sampler exploits a 2-tap FFE and a 2-tap DFE to compensate for ISI of the TIA, ensuring correct data recovery. Timing criteria of DFE loop is achieved up to 30 GBaud by optimizing the clock-to-Q delay of slicers. The RX is implemented in 28-nm CMOS process and is wirebonded to a commercial photodiode. Optical measurement results at 48-Gb/s PAM4 show the RX achieves −5.1-dBm sensitivity at 2.4e-4 BER using 61.4 mW, with only 13.1 mW contributed from the TIA, resulting in 1.28-pJ/bit (0.27 pJ/bit for TIA only) efficiency.