A $94\text{fs}_{\text{rms}}$-Jitter and −249.3dB FoM 4.0GHz Ring-Oscillator-Based MDLL with Background Calibration of Phase Offset and Injection Slope Mismatch

This paper presents a ring oscillator (RO)-based multiplying delay- locked loop (MDLL) with frequency and slope detector (FSD) that can control both the oscillation frequency and the injection signal slope. By comparing characteristics of two consecutive transitions of the RO before and after the injection, the FSD distinguishes the cause of error, i.e., mismatch in period or slope. Hence, it can individually drive two loops; 1) for locking the steady-state frequency of the RO and 2) for matching the transition slope of the reference edge to that of the internal node of the RO. As the proposed FSD efficiently mitigates each jitter source, the chip, implemented in 40nm CMOS, shows an integrated rms jitter of $94\text{fs}_{\mathrm{r}\mathrm{m}\mathrm{s}}$ at 4GHz, achieving a FoM of -249.3dB.