First Experimental Demonstration of Hybrid Gain Cell Memory with Si PMOS and ITO FET for High-speed On-chip Memory

This work experimentally demonstrates hybrid gain cell memory with Si PMOS as read transistor and ITO FET as write transistor integrated monolithically on the same chip. With Si PMOS as the read transistor, hybrid gain cell memory has the benefits of high read speed, counterbalanced capacitive coupling, optimized state allocation, and superb bias stress stability. Fabricated Si PMOS has mobility of 86.4 cm²/Vs and the ALD ITO FET has positive VTH = 0.75 V and excellent SS = 65 mV/dec. Hybrid gain cell shows measured retention of 5,000 sec under OV WWL standby voltage. Excellent stability of < 12 mV shift for Si PMOS and ITO FET under 1,000 sec bias stress in standby mode is achieved.