Dyamond: A 1T1C DRAM In-memory Computing Accelerator with Compact MAC-SIMD and Adaptive Column Addition Dataflow

We propose Dyamond, a ITIC DRAM in-memory computing accelerator with column addition (CA) dataflow, for high density and energy efficiency. LSB-CA minimizes ADC readouts to increase energy efficiency. MSB-CA with signal-enhanced MAC and signal-shifted ADC enhances SQNR, improving energy efficiency. A switchable sense amplifier reduces read energy for low-power in-memory arithmetic SIMD. Dyamond is fabricated in 28nm CMOS technology, integrating 27Mb DRAM memory within a 6.48mm² die area. It achieves 27.2 TOPS/W peak energy efficiency and outstanding performance in advanced models (ResNet BERT, GPT-2).