ZeroVex: A Scalable and High-performance RISC-V Vector Processor Core for Embedded Systems

This paper presents ZeroVex, a scalable and high-performance RISC-V vector processor core designed specifically for embedded devices. The architecture employs a portion of the RISC-V v1.0 vector ISA expansion specifically for edge machine learning inference. The ZeroVex microarchitecture consists of several similar lanes that operate concurrently. Every lane has vector function units and a portion of the vector register file, allowing for expandability. Furthermore, it utilizes multiple parallel execution strategies that depart from the traditional vector architecture to achieve a significant degree of parallelism. The experimental results show that ZeroVex, with a VLEN of 256-bit and 8 channels, achieves a speedup of 160x-235x and improves energy efficiency by 30x.