SLICE Matrix: A Memory Access Scheduling Policy for Multicore Network Processors

In a network processor, multiple processor cores share a centralized memory, whose latency and bandwidth easily become bottlenecks. Unlike CPUs or GPUs, network processors serve for packets and do not execute programs in units of tasks or processes. Therefore, a dedicated scheduling policy of centralized memory must be designed for packets. In this paper, we propose an efficient memory access scheduling policy when a great number of packets access centralized memory. Compared with traditional scheduling strategies such as synchronous RR and synchronous DRR, it performs dynamic scheduling based on real-time situations of packets and calculates the scheduling result through the packet status matrix. As a result, it can reduce the average memory access latency by 29.44%, thereby increasing the packet bandwidth of the network processor system by 5.74%.