Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs

The major challenge when designing multipliers for FPGAs is to address several tradeoffs: On the one hand at the performance level and on the other hand at the resource level utilizing DSP blocks or lookup tables (LUTs). With DSPs being a relatively limited resource, the problem of under- or over-utilization of DSPs has previously been addressed by the concept of multiplier tiling, by assembling multipliers from DSPs and small supplemental LUT multipliers. But there had always been an efficiency gap between tiling-based multipliers and radix-4 Booth-Arrays. While the monolithic Booth-Array was shown to be considerably more efficient in terms of L UT- resources on many modern FPGA-architectures, it typically possess a significantly higher critically path delay (or latency when pipeline d) compared to multipliers designed by tiling. This work proposes and analyzes the use of smaller Booth-Arrays as sub-multipliers that are integrated into existing tiling-based methods, such that better tradeoff points between area and delay can be reached while utilizing a user-specified number of DSP blocks. It is shown by synthesis experiments, that the critical path delay compared to large Booth-Arrays can be reduced, while achieving significant reductions in LUT-resources compared to previous tiling.