Unveiling DRAM Failures Across Different CPU Architectures in Large-Scale Datacenters

Memory failures frequently lead to server break-downs in large-scale datacenters, with uncorrectable errors (UEs) serving as primary indicators of defects in Dual Inline Memory Modules (DIMMs). Existing approaches mainly focus on predicting UEs using correctable errors (CEs), but often neglect the relationships of these errors across various CPU architectures, especially in the context of Error Correction Code (ECC). In this paper, we explore the correlation between CEs and UEs across different CPU Architectures, such as x86 and ARM. Our analysis reveals distinctive failure patterns in memory specific to each processor platform. Leveraging Machine Learning (ML) techniques on production datasets, we demonstrate that our approach substantially enhances prediction performance up to 15% in F1-score compared to the existing alaorithm.