Low-Area FPGA Implementation of Negative Exponential Function for ANFIS Design

one of the successful machine learning methods that has been used in many different applications is the adaptive neuro-fuzzy inference system. The selection of membership function type is fundamental to ANFIS performance, as it has the greatest impact on the accuracy and computing complexity of the ANFIS-based model that is created. To assist researchers in selecting the appropriate membership functions for their ANFIS models, an in-depth investigation is desperately needed. One of the essential membership functions used in the ANFIS system is the exponential function. Thus, the function of the exponential membership function is investigated in this paper. Improved implementations of this function are becoming more and more needed, as the current methods have high time and space needs. Consequently, a new, more effective solution is developed in this study using a partial exponential function reduction technique. The FPGA platform Spartan-3A DSP 3400A is used to implement this method. With 28 look-up tables (LUTs) and 25 occupied slices, it is shown that this exponential function implementation provides precise performance with little space use. In addition, the method uses just one clock cycle while achieving a high throughput. The results show that the suggested approach performs better than earlier techniques.