An Area-Efficient Low-Power Fully Non-Volatile Full-Adder using Reconfigurable Logic

The miniaturization of CMOS results in high static power consumption in traditional computer system. Logic-in-memory (LIM) architecture based on emerging non-volatile memory (NVM) can significantly reduce static power consumption by embedding computing and logic functions into NVM. Magnetic tunnel junction (MTJ) is considered as one of the most promising candidates for LIM circuits owing to its high speed, nearly infinite endurance, and 3D back-end integration technology. This paper introduces a reconfigurable LIM circuit integrating spin transfer torque based MTJs (STT-MTJs). Unlike the conventional non-volatile full-adders (NV-FAs) that perform the “Sum” and “Co” operations with two sub-circuits, the proposed circuit can perform both operations. Simulation results based on 28 nm CMOS process design kit and a perpendicular STT-MTJ compact model show that the proposed NV-FA has the advantages of small area and low power consumption.