Energy-Efficient Vertically Stacked NSFET-Based CTM for Logic in-Memory Computing

This work highlights the implementation of Boolean logic functions (AND, OR, NOR, XOR, and XNOR) in two steps for logic in-memory computing applications through a double gate vertically stacked nanosheet-based charge-trapping memory (DG-NSFET-CTM). The charge-trapping memory operation with high-κ blocking oxide material is based on the Fowler-Nordheim (FN) tunneling mechanism at a lower voltage (± 6V), which makes the device energy efficient. The device achieves a memory window of ~1.77 V and consumes less energy (~45.5 fJ) during inference. The work also shows the effect of vertically stacking nanosheets on the implementation of logic gates and energy consumption. The obtained results confirm the proposed dual gate NSFET-based CTM could be a promising candidate for next-generation in-memory computing.