Polynomial Formal Verification of Multi-Valued Logic Circuits within Constant Cutwidth Architectures

Formal verification is essential for circuit correctness. Extending binary logic verification to Multi-Valued Logic (MVL) presents challenges due to encoding challenges. Answer Set Programming (ASP) enables compact MVL circuit encoding. In this paper, we propose a Polynomial Formal Verification (PFV) approach for MVL circuits with a constant cutwidth. It employs a divide-and-conquer algorithm to decompose circuits into subcircuits, each representing an output, where ASP is used to encode and verify the subcircuits. The approach reduces verification complexity to the circuit's cutwidth, independent of input bitwidth, ensuring linear time verification for circuits with constant cutwidth. We validate our approach using adder architectures, as many adder architectures have a constant cutwidth. Empirical experiments involve various adder architectures and different logic levels.