Randomness Assessments for PDL-based TRNG on FPGA

This paper investigates the enhancement of True Random Number Generators (TRNGs) in Field-Programmable Gate Arrays (FPGAs) through Programmable Delay Logic (PDL). We examine how PDL influences the entropy quality and performance of TRNGs by controlling Ring Oscillators (ROs). Our study, conducted using Xilinx Artix-7 7A100T and Kintex Ultrascale KU040 devices, utilizes NIST SP 800-22 tests to evaluate different PDL settings. Findings demonstrate that precise PDL configurations are crucial for optimizing TRNG performance and security. This research underlines the importance of PDL in developing robust FPGA-based security systems, offering significant insights into effective digital system security enhancements.