FPGA Implementation of Hardware-based Demand Paging on RISC- V Architecture

The Operating System (OS) manages disk I/O operations through a dedicated software stack. Traditionally, the overhead of this software stack was considered negligible for storage systems based on hard disks, due to their inherently long access latencies. However, the advent of low-latency Solid State Drives (SSDs) has significantly increased the impact of OS software overhead on I/O processing efficiency. To address this, hardware-based demand paging has been proposed as a solution to reduce software overhead associated with handling page faults. Though theoretically advantageous, the real-world efficacy of hardware-based demand paging has been mostly untested, with investigations largely confined to simulations. This paper introduces an implementation and evaluation of hardware-based demand paging on an FPGA-based RISC-V system, assessing its viability. Our findings indicate that, relative to traditional OS-based methods, implementing hardware-based demand paging substantially reduces software overhead in actual hardware scenarios, improving the performance of the FIO read random benchmark by up to 85.4%.