A 6 to 21 GHz CMOS Low Noise Amplifier Using Inductive-Peaking and Wideband Matching Techniques

This work presents the design of a wideband low noise amplifier (LNA), which simulates in 130-nm CMOS process. The wideband input impedance matching is realized by four-order bandpass filter. The LNA expands the bandwidth (BW) by the peaking load. To further broaden the gain response, the three-stage LNA is also stagger tuned. Furthermore, the off-chip bonding wire inductors replace the on-chip source degenerate inductors, improving the integration of the LNA. The proposed LNA has a maximum gain of 20 dB with its 3 dB BW ranging from 6 to 21 GHz, a minimum noise figure (NF) of 2.3 dB, and an IIP3 of −8.4 dBm. It consumes a DC dissipation power of 33.5 mW from 1.2 V supply voltage and achieves S11 and S22 below −10 dB, gain flat of ±0.4 dB, and occupies chip area of 0.98 mm
²
including pads.