Improved Hardware Accelerator for Object Detection

Driven by the need for increased precision, Convolutional Neural Networks (CNNs) have surpassed traditional platforms, leading to the exploration of alternatives such as GPUs, ASICs, and notably, Field Programmable Gate Arrays (FPGAs). FPGAs are perfect for complicated CNN acceleration because they combine low latency, energy efficiency, and flexibility in a unique way. FPGA development has been made easier by High-Level Synthesis (HLS) tools, which have improved the effectiveness and quality of designs. The optimization potential of Xilinx Deep Learning Processing Units (DPUs) within FPGA-based CNN acceleration is examined in this study, with attention paid to changing the internal parameters to suit the needs. An overview of related work is presented, focusing on the previous attempts at building and improving such Hardware accelerators. The proposed workflow makes use of the flexibility provided by DPUs. In addition to the results showing effectiveness of DPUs, insights into their architecture and performance characteristics are presented.