Hardware Trojan Design and Analysis in FPGA an Introductory Exploration

Hardware Trojan (HT) has been a rapidly developing area of interest in the hardware security world. They have impacted the Integrated Chips (IC) industry and increased the standards of testing and detection of malicious hardware. Although a wide range of literature has contributed to enhancing the design of hardware trojans and detection algorithms to identify trojans, scarce academic work is found in the area of hardware trojans in Field Programmable Gated Arrays (FPGAs). This project aims to understand the design and implementation of hardware trojans from an attacker's perspective, encompassing the technique of hardware trojan design, the potential attack vector, and the stealthiness of the hardware trojan. A state-machine-based hardware trojan is designed to attack the Universal Asynchronous Receive Transmitter UART. Firmware updates for a wide range of medical devices happen through serial communication or wireless transfer. Attacking the UART of these devices could corrupt the firmware of the device, which could corrupt the boot loader path, resulting in the malfunction of the device. This poses a very dangerous threat, especially in the medical device field, where less attention is given to security. The paper presents a demonstrative example of a hardware trojan attacking Booth's algorithm.