Custom Design of 16 Bit RISC Processor Using Low Power Pipelining

This work presents a full-custom 16-bit low-power pipelined RISC processor, with a primary focus on achieving low power consumption while enhancing overall performance. The processor employs a four-stage pipelining technique, enabling concurrent execution of multiple instructions. The pipeline stages consist of instruction fetch, decode, execute, and write-back, and it operates on both positive and negative edges. The top module of the processor incorporates various blocks, including the Arithmetic Logic Unit, Barrel Shifter, Decoder, and Universal Shift Registers. To minimize power consumption, the top module will be implemented in various styles before deciding upon the architecture which uses less power. An Arithmetic Logic Unit is integrated as a forwarding unit, setting this architecture apart from traditional Harvard or Von Neumann architectures. Verilog HDL serves as the foundational language, with comprehensive implementation and analysis of the top module, RTL code, timing diagrams, and Netlist generation performed using the XILINX ISE DESIGN tool.